1. Technical Field
The present invention relates generally to processing system memory subsystems, and more particularly, to a diagnostic memory module that provides programmable functionality to observe and/or alter memory module behavior.
2. Description of the Related Art
Memory subsystems in present-day computer systems include multiple memory modules that provide system memory. During design and manufacture of such computer systems and their elements such as processor blade units or motherboards, and in particular, dedicated memory controller units and processors incorporating a memory controller unit, it is desirable to evaluate features such as error detection and error correction, as well as design margins for memory performance such as read cycle delay and write cycle timing margins.
However, performance of an actual memory device is typically fixed by design and therefore techniques for testing the error detection/correction mechanisms have traditionally been limited to methods such as using “known bad” modules, or techniques such as forcing parity errors by disabling parity information. Software has long been available for performing system memory tests, but such tests are performed on memory implementations that are fixed by design, or are externally manipulated in a laboratory environment. Timing margins have been evaluated by changing external loads or terminators, but such techniques are time-consuming and provide only a crude evaluation of the actual timing margins. Furthermore, such methodologies do not reveal information describing behavior internal to a memory module, but only the behavior of the memory module when influenced by external loading.
Load devices that can be directly inserted in a standardized memory module socket have provided some simplification of memory controller and system design evaluation, in that test points can be provided while still providing a nominal load equivalent to an actual memory device. However, such test modules typically have fixed signal loading values and replace a memory device with only passive loads and test points, in which the passive loads approximate the loading of an actual memory module. In order to change the loading, the inserted load device would have to be removed and another load device with different loading characteristics would have to be inserted. The test points provided are also not located at the exact location of storage that can be written to and read from, and therefore only provide for measurement of external memory bus signals. Further, testing error detection/correction mechanisms using such a device is still limited to techniques such as externally loading a test point until a fault occurs.
It is therefore desirable to provide a method and apparatus for evaluating memory controller and memory subsystem designs that provide flexible manipulation of the memory subsystem behavior and information about signal behavior at the actual location of the storage. It would further be desirable to provide information about signal behavior internal to a memory module.